15 . 0 Custom Integrated Circuits
نویسندگان
چکیده
The research goal of this project is to devise CAD techniques for the performancedirected synthesis of digital VLSI circuits, focused on digital signal processing applications. The main goal is to develop expert system techniques that are designed to yield optimal performance in these signal processing systems through a fundamental approach to the design task. An overall design involves the specification of multiple constraint domains corresponding to various levels of representation. These facets include the function, architecture, logic, circuit, layout, and device levels. They must be coherently related so that each is a consistent and correct projection of the complete design onto a single facet or type of representation. This viewpoint has led to three major concerns:
منابع مشابه
2012 IEEE Custom Integrated Circuits Conference (CICC 2012) : San Jose, California, USA, 9 - 12 September 2012
متن کامل
Application-Specific Integrated Circuits (ASICS)
5 ASIC Technologies 8 5.1 Full Custom Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5.2 Standard Cell ASIC Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5.3 Gate Array ASIC Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.4 Sea-of-Gates ASIC Technology . . . . . . . . . . . ....
متن کامل15 . 0 Custom Integrated Circuits Academic and Research Staff
The overall goal of VLSI CAD research is to provide the means to produce custom integrated circuits correctly, quickly, and economically. In the past, correctness applied only to the desired function, but there is increasing need to design to a performance specification, expressed in terms of speed, circuit area, and power. In this research group, the main emphasis is on CAD tools for performan...
متن کاملA 2.5V 10b 120 Msample/s CMOS pipelined ADC with high SFDR - Custom Integrated Circuits Conference, 2002. Proceedings of the IEEE 2002
A 10b multibit-per-stage pipelined ADC incorporating merged-capacitor switching (MCS) technique achieves better than 53 dB SNDR at 120 MSample/s and 54 dB SNDR and 68 dB SFDR for input frequencies up to Nyquist at 100 MSample/s. The measured DNL and INL are f0.40 LSB and f0.48 LSB, respectively. The ADC fabricated in a 0.25 pm CMOS occupies 3.6 mm2 active die area and consumes 208 mW under a 2....
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